In the manufacture of multi-layer thick film circuits, successive layers of circuitry comprising conductors and components are electrically and physically isolated from one another by one or more intervening layers of dielectric material. To provide adequate isolation, the dielectric layer must be fairly thick, particularly where the top circuit layer includes components that are designed to be laser trimmed. Printing a thick dielectric layer is also desirable for process considerations, as thinner prints are prone to the formation of undesirable pin-holes, and such pin-holes are prone to propagate through successive layers of thin dielectric prints. However, thick layers of dielectric are problematic because they tend to spread beyond the intended print pattern, reducing the definition of dielectric features such as via openings and solder stops. Although dielectric formulations can be modified to reduce spreading, this also tends to produce pin-holes in the resulting dielectric layer. Consequently, circuit designers must contend with an engineering tradeoff between print thickness and feature definition. In a typical design compromise, the dielectric is printed at less than the desired thickness, and the via openings are enlarged and the solder stops are pulled back to accommodate a certain amount of dielectric layer spreading. Increased dielectric thickness is then achieved by printing one or more additional dielectric layers atop the initial dielectric layer. Obviously, this design approach is not particularly desirable, since extra large dielectric features limit circuit density on the upper dielectric layer, thin printing layers are prone to pin-holing, and extra printing and firing steps increase cost and reduce manufacturing throughput.